Job Description

About the Job You’re Considering

We’re looking for a collaborative Senior Mixed-Signal Design Verification Engineer to help shape the future of SoC development. In this role, you’ll contribute to the validation of high-performance ARM-based systems, working across digital and analog domains. You’ll join a supportive team that values diverse perspectives, continuous learning, and innovative problem-solving.

Your Role

• Develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs with embedded CPUs and mixed-signal interfaces.
• Contribute to AMS and power-aware verification efforts across multiple projects, ensuring robust and efficient validation.
• Create detailed test plans and coverage metrics from design specifications, and execute both block- and chip-level tests.
• Automate verification workflows using PERL and Python to streamline test generation and debugging.
• Collaborate with design engineers to analyze and resolve RTL and gate-level simulation issues.
• Validate low-power design intent using UPF or CPF through targeted test cases.
• Partner with architects to simulate real-world use cases and ensure system-level functionality.

Your Skills and Experience

• Bachelor’s degree or higher in Electrical or Computer Engineering, with 7+ years of experience.
• Deep expertise in SystemVerilog, UVM, and SV Assertions, with a strong foundation in Verilog-HDL and scripting.
• Proven success in verifying ARM Cortex-based SoCs and working with interfaces such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficient with Cadence tools (NCVerilog, NCSIM, Simvision), AMS simulation environments, and experience with SDF-annotated simulations and linting tools.
• Strong analytical and communication skills, with a self-driven, collaborative approach to problem-solving and automation using Python and PERL.

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